汽车电子研究中心

研究方向 / 智能驾驶
研究方向简介 / Research Direction

主要针对智能驾驶车辆和相关关键技术发展的需求,将通信安全、激光雷达、机器视觉、主动安全、节能等技术运用到车辆系统中,开展系统性的多学科交叉研究。
1.感知
针对车用雷达和机器视觉的信息融合技术和视觉探测与测量技术中空间三维信息构建等新技术进行研究
2.自主驾驶决策
基于深度强化学习的框架,构建自动驾驶策略学习算法模型,并利用并行计算提高数据集的训练效率。
3. 车联网通信安全
对车联网的接入身份认证、安全行驶、计费管理、交通管理、数据通信等进行数据加解密,身份认证、密钥分发的研究。
4.节能驾驶
通过路径规划和车速调整来实现节能的研究,结合交通大数据环境,实现电动汽车的智能节能,从而从整个城市的层面实现节能。

通用深度学习处理器体系结构 / Selected Projects

为解决传统芯片体系结构对深度学习技术在计算与数据存储能力上的瓶颈,专用定制人工智能芯片(ASIC) 依靠其强大的运算能力、先进的制造技术以及与CPU, GPU, FPGA平台完全不同的处理器体系结构,对神经网络计算进行大幅度加速,并降低功率消耗。本项目从并行计算、在线训练、神经元随机性引入等几方面对深度学习基本运算进行优化,在此基础上设计出具有并行性、高内存带宽、低功耗的智能芯片。在应用模式上,该芯片同时支持监督学习与强化学习,从而大幅度加速智能系统的感知与决策能力。










成果 / Intellectual Properties

代表性论文 / Selected Papers

(1) Wang, Zheng(#)(*), Chattopadhyay, Anupam: High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip, ISBN: 978-981-10-1073-6, Springer, 2017.

(2) Wang, Zheng(#),  Chen, Yi,  Aakash, Patil, Jayabalan, Jayasanker, Zhang, Xueyong, Chang, Chip Hong and Basu, Arindam(*): Current Mirror Array: A novel circuit topology for combining Physical Unclonable Function and Machine Learning, IEEE Transactions on Circuits and Systems I: Regular Papers, 2017

(3) Wang, Zheng(#)(*), Chen,Yi, Patil, Aakash, Chang, Chip Hong and Basu, Arindam: Current Mirror Array: a Novel Lightweight Strong PUF Topology with Enhanced Reliability, International Symposium on Circuits & Systems (ISCAS), Baltimore, 2017.5.28-2017.5.31

(4) Wang, Zheng(#)(*), Kanwal, Shazia, Wang, lai and Chattopadhyay, Anupam: Automated High-level Modeling of Power, Temperature and Timing Variation for Microprocessor, KMUTNB: International Journal of Applied Science and Technology, 2017

(5) Wang, Zheng(#)(*)Karakonstantis, GeorgiosChattopadhyay, Anupam: A low overhead error confinement method based on application statistical characteristicsDesign Automation and Test in Europe (DATE)Dresden2016.3.1 4-2016.3.18

(6) Wang, Zheng(#)(*)Littarru, AlessandroUgwu, Emmanuel IkechukwuKanwal, ShaziaChattopadhyay, Anupam: Reliable many-core system-on-chip design using K-Node fault tolerant graphsIEEE Computer Society Annual Symposium on VLSI (ISVLSI)United States2016.7.11-2016.7.13

(7) Wang, Zheng(#)(*)Yang, LiuChattopadhyay, Anupam: Architectural reliability estimation using design diversityInternational Symposium on Quality Electronic Design (ISQED)Santa Clara2015.3.2-2015.3.4

(8)  Wang, Zheng(#)(*)Xie, HuiChafekar, SaumitraChattopadhyay, Anupam: Architectural error prediction using probabilistic error masking matricesAsia n Symposium on Quality Electronic Design (ASQED)Kuala Lumpur2015.8.4-2015.8 .5

(9) Wang, Zheng(#)(*)Chen, ChaoSharma, PiyushChattopadhyay, Anupam: System-level reliability exploration framework for heterogeneous MPSoCGreat Lakes Symposium on VLSI (GLSVLSI)Houston2014.5.21-2014.5.23

(10) Wang, Zheng(#)(*)Paul, GoutamChattopadhyay, Anupam: Processor design with asymmetric reliabilityIEEE Computer Society Annual Symposium on VLSI (ISVLSI)Tampa2014.7.9-2014.7.11

(11) Wang, Zheng(#)(*)Li, RenlinChattopadhyay, Anupam: Opportunistic redundancy for improving reliability of embedded processorsInternational Design & Test Symposium (IDT)Marrakech2013.12.16-2013.12.18

(12) Wang, Zheng(#)(*)Singh, KapilChen, ChaoChattopadhyay, Anupam: Accurate and efficient reliability estimation techniques during adl-driven embedded processor designDesign Automation and Test in Europe (DATE)Grenoble2013.3 .18-2013.3.22

(13) Wang, Zheng(#)(*)Wang, LaiXie, HuiChattopadhyay, Anupam: Power modeling and estimation during ADL-driven embedded processor designInternational Conference on Energy Aware Computing Systems & Applications (ICEAC)Istanbul2013.12.16-2013.12.18

(14) Wang, Zheng(#)(*)Chen, ChaoChattopadhyay, Anupam: Fast reliability exploration for embedded processors via high-level fault injectionInternational Symposium on Quality Electronic Design (ISQED)Santa Clara2013.3.4-2013.3 .6

(15) Wang, Zheng(#)(*)Wang, XiaoChattopadhyay, AnupamRakosi, Zoltan E.: ASIC synthesis using Architecture Description LanguageInternational Symposium on VLSI Design, Automation & Test (VLSI-DAT)Hsinchu2012.4.23-2012 .4.25

(16) Constantin, Jeremy(#)(*)Wang, ZhengKarakonstantis, GeorgiosChattopadhyay, AnupamBurg, Andreas: Statistical fault injection for impact-evaluation of timing errors on application performanceDesign Automation Conference (DAC)Austin2016.6.5-2016.6.9

(17) Bian, Song(#)(*)Shintani, MichihiroWang, ZhengHiromoto, MasayukiChattopadhyay, AnupamSato, Takashi: Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node ControlAsian Test Symposium (ATS)Hiroshima2016.11.21-2016.11.24

(18) Marcu, Marius(#)(*)Boncalo, OanaGhenea, MadalinAmaricai, AlexandruWeinstock, JanLeupers, RainerWang, ZhengGeorgakoudis, GiorgisNikolopoulos, Dimitrios S.Cernazanu-Glavan, CosminBara, LucianIonascu, Marian: Low-cost hardware infrastructure for runtime thread level energy accountingInternational Conference on Architecture of Computing Systems (ARCS)Nuremberg2016.4.4-2016.4.7

(19) Cernazanu-Glavan, Cosmin(#)(*)Marcu, MariusAmaricai, AlexandruFedeac, StefanGhenea, MadalinWang, ZhengChattopadhyay, AnupamWeinstock, JanLeupers, Rainer: Direct FPGA-based power profiling for a RISC processorInstrumentation and Measurement Technology Conference (I2MTC) Pisa2015.5.11-2015.5.14

(20) Rakosi, Zoltan Endre(#)(*)Wang, ZhengChattopadhyay, Anupam: Adaptive energy-efficient architecture for WCDMA channel estimationInternational Conference on Reconfigurable Computing and FPGAs (ReConFig)Cancun2011.11.30-2011.12.2

(21) Rákossy, Zoltán Endre(#)Wang, ZhengChattopadhyay, Anupam(*): High-level design space and flexibility exploration for adaptive, energy-efficient WCDMA channel estimation architecturesInternational Journal of Reconfigurable Computing2012.01.01, 2012

代表性专利 / Selected Patents