汽车电子研究中心
Research / On-board Computing Platform
Research Direction

To be updated

Generic Processor Architecture for Neural Networks

Deep learning technique and applications involve a tremendous amount of computation, which goes beyond the limit of general purpose computing platform. Recently, GPU and FPGA-based machine learning platform deliver higher computing power due to their internal parallelism. However, such high-level synthesis oriented acceleration system incurs a large amount of data transmission between the host machine and the accelerator modules, which lead to huge waste of power consumption and reduce the processing throughput as well. Consequently, customized processor architecture targeting machine learning become the focus of architecture society recently.

This project constructs generic and reconfigurable computing platform by exploring the features of neural networks, which includes the following topics:

1. Support the operating modes as supervised learning and reinforcement learning.
2. Parallel computing with distributed storage.
3. Introduce randomness as a key feature of neuron nets, which helps to expand the dimension of neurons significantly.
4. Fast and online training with customized hardware logic such as back propagation and extreme learning machine.
5. Introduce programmability and reconfigurability to increase the generalization of the architecture.
6. Reduce the power consumption while maintaining acceptable reliability level.

Intellectual Properties

Selected Papers

(1) Wang, Zheng(#)(*), Chattopadhyay, Anupam: High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip, ISBN: 978-981-10-1073-6, Springer, 2017.

(2) Wang, Zheng(#),  Chen, Yi,  Aakash, Patil, Jayabalan, Jayasanker, Zhang, Xueyong, Chang, Chip Hong and Basu, Arindam(*): Current Mirror Array: A novel circuit topology for combining Physical Unclonable Function and Machine Learning, IEEE Transactions on Circuits and Systems I: Regular Papers, 2017

(3) Wang, Zheng(#)(*), Chen,Yi, Patil, Aakash, Chang, Chip Hong and Basu, Arindam: Current Mirror Array: a Novel Lightweight Strong PUF Topology with Enhanced Reliability, International Symposium on Circuits & Systems (ISCAS), Baltimore, 2017.5.28-2017.5.31

(4) Wang, Zheng(#)(*), Kanwal, Shazia, Wang, lai and Chattopadhyay, Anupam: Automated High-level Modeling of Power, Temperature and Timing Variation for Microprocessor, KMUTNB: International Journal of Applied Science and Technology, 2017

(5) Wang, Zheng(#)(*)Karakonstantis, GeorgiosChattopadhyay, Anupam: A low overhead error confinement method based on application statistical characteristicsDesign Automation and Test in Europe (DATE)Dresden2016.3.1 4-2016.3.18

(6) Wang, Zheng(#)(*)Littarru, AlessandroUgwu, Emmanuel IkechukwuKanwal, ShaziaChattopadhyay, Anupam: Reliable many-core system-on-chip design using K-Node fault tolerant graphsIEEE Computer Society Annual Symposium on VLSI (ISVLSI)United States2016.7.11-2016.7.13

(7) Wang, Zheng(#)(*)Yang, LiuChattopadhyay, Anupam: Architectural reliability estimation using design diversityInternational Symposium on Quality Electronic Design (ISQED)Santa Clara2015.3.2-2015.3.4

(8)  Wang, Zheng(#)(*)Xie, HuiChafekar, SaumitraChattopadhyay, Anupam: Architectural error prediction using probabilistic error masking matricesAsia n Symposium on Quality Electronic Design (ASQED)Kuala Lumpur2015.8.4-2015.8 .5

(9) Wang, Zheng(#)(*)Chen, ChaoSharma, PiyushChattopadhyay, Anupam: System-level reliability exploration framework for heterogeneous MPSoCGreat Lakes Symposium on VLSI (GLSVLSI)Houston2014.5.21-2014.5.23

(10) Wang, Zheng(#)(*)Paul, GoutamChattopadhyay, Anupam: Processor design with asymmetric reliabilityIEEE Computer Society Annual Symposium on VLSI (ISVLSI)Tampa2014.7.9-2014.7.11

(11) Wang, Zheng(#)(*)Li, RenlinChattopadhyay, Anupam: Opportunistic redundancy for improving reliability of embedded processorsInternational Design & Test Symposium (IDT)Marrakech2013.12.16-2013.12.18

(12) Wang, Zheng(#)(*)Singh, KapilChen, ChaoChattopadhyay, Anupam: Accurate and efficient reliability estimation techniques during adl-driven embedded processor designDesign Automation and Test in Europe (DATE)Grenoble2013.3 .18-2013.3.22

(13) Wang, Zheng(#)(*)Wang, LaiXie, HuiChattopadhyay, Anupam: Power modeling and estimation during ADL-driven embedded processor designInternational Conference on Energy Aware Computing Systems & Applications (ICEAC)Istanbul2013.12.16-2013.12.18

(14) Wang, Zheng(#)(*)Chen, ChaoChattopadhyay, Anupam: Fast reliability exploration for embedded processors via high-level fault injectionInternational Symposium on Quality Electronic Design (ISQED)Santa Clara2013.3.4-2013.3 .6

(15) Wang, Zheng(#)(*)Wang, XiaoChattopadhyay, AnupamRakosi, Zoltan E.: ASIC synthesis using Architecture Description LanguageInternational Symposium on VLSI Design, Automation & Test (VLSI-DAT)Hsinchu2012.4.23-2012 .4.25

(16) Constantin, Jeremy(#)(*)Wang, ZhengKarakonstantis, GeorgiosChattopadhyay, AnupamBurg, Andreas: Statistical fault injection for impact-evaluation of timing errors on application performanceDesign Automation Conference (DAC)Austin2016.6.5-2016.6.9

(17) Bian, Song(#)(*)Shintani, MichihiroWang, ZhengHiromoto, MasayukiChattopadhyay, AnupamSato, Takashi: Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node ControlAsian Test Symposium (ATS)Hiroshima2016.11.21-2016.11.24

(18) Marcu, Marius(#)(*)Boncalo, OanaGhenea, MadalinAmaricai, AlexandruWeinstock, JanLeupers, RainerWang, ZhengGeorgakoudis, GiorgisNikolopoulos, Dimitrios S.Cernazanu-Glavan, CosminBara, LucianIonascu, Marian: Low-cost hardware infrastructure for runtime thread level energy accountingInternational Conference on Architecture of Computing Systems (ARCS)Nuremberg2016.4.4-2016.4.7

(19) Cernazanu-Glavan, Cosmin(#)(*)Marcu, MariusAmaricai, AlexandruFedeac, StefanGhenea, MadalinWang, ZhengChattopadhyay, AnupamWeinstock, JanLeupers, Rainer: Direct FPGA-based power profiling for a RISC processorInstrumentation and Measurement Technology Conference (I2MTC) Pisa2015.5.11-2015.5.14

(20) Rakosi, Zoltan Endre(#)(*)Wang, ZhengChattopadhyay, Anupam: Adaptive energy-efficient architecture for WCDMA channel estimationInternational Conference on Reconfigurable Computing and FPGAs (ReConFig)Cancun2011.11.30-2011.12.2

(21) Rákossy, Zoltán Endre(#)Wang, ZhengChattopadhyay, Anupam(*): High-level design space and flexibility exploration for adaptive, energy-efficient WCDMA channel estimation architecturesInternational Journal of Reconfigurable Computing2012.01.01, 2012

Selected Patents