汽车电子研究中心
Research / On-board Computing Platform
Research Direction

To be updated

SoC FPGA cluster design and optimization technology for deep learning

The heterogeneous computing mode of FPGA+CPU combines the software programmability of the CPU and the hardware programmability of the FPGA. It is more flexible, adapts to a wider range of scenarios, and has a faster development speed. However, due to the limited hardware resources of the single-board FPGA, it is complicated In the implementation of deep neural network, single-board FPGA is difficult to obtain high throughput. In order to obtain higher task throughput, this project proposes a general-purpose and scalable FPGA heterogeneous cluster structure based on pipelines, which can evenly deploy tasks in different layers according to the running time or computational load of different layers of the deep neural network. In the construction cluster, thereby maximizing throughput and energy efficiency.

Intellectual Properties

Selected Papers

(1)      Cuiping Shao; Huiyun Li*; Identifying Single-Event Transient Location Based on Compressed Sensing, IEEE Transactions on Very Large Scale Integration Systems, 2018, 26(4): 768-777.  (SCI  JCR 2区)

(2)      Cuiping Shao; Huiyun Li*; Jiayan Fang; Qihua Deng; An Error Location and Correction Method for Memory Based on Data Similarity Analysis, IEEE Transactions on Very Large Scale Integration Systems, 2019, 27(10): 2354-2364. (SCI JCR 2区)

(3)      Cuiping Shao; Huiyun Li; Zheng Wang; Jiayan Fang; A Generic Block-Level Error Confinement Technique for Memory Based on Principal Component Analysis, Applied Sciences, 2019, 9(22): 4733-4751. (SCI JCR 2区)

Selected Patents

(1)      Cuiping Shao; Huiyun Li; Jiayan Fang; Error correction methods, devices, equipment and media for reading data in the memory; Patent No: ZL201810576516.9, Authorization announcement date:2019.10.29.

(2)      Huiyun Li; Cuiping Shao; Fenfen Liu; Chip single event effect detection method and device; Patent No: ZL201610480725.4, Authorization announcement date:2019.02.12.

(3)      Cuiping Shao; Huiyun Li; Guoqin Xu; Method and device for evaluating hardware safety based on RSA algorithm; Patent No: ZL201510646478.6, Authorization announcement date:2019.08.10.

(4)      Cuiping Shao; Huiyun Li; Guoqin Xu; Method and device for strengthening security chip against error injection attack; Date of Application: 2015.06.24; Patent No: ZL201510355203.7, Authorization announcement date:2018.08.03.

(5)      Cuiping Shao; Huiyun Li; Guoqin Xu; Method and device for manufacturing 3D crypto chip resistant to error injection attack; Date of Application: 2015.10.29; Patent No: ZL201510716393.0, Authorization announcement date: 2019.01.25.